1. Technical Field
The present invention relates to a test apparatus for testing a memory and to a repair analysis method.
2. Related Art
A test apparatus that tests a memory writes prescribed data to the memory under test, reads the written data, and compares the read data to an expected value. Furthermore, the test apparatus writes fail data, which indicates that the read data does not match the expected value, to an address fail memory (AFM). The test apparatus performs a repair analysis of the memory under test based on the fail data written to the AFM, as shown in Patent Document 1, for example.    Patent Document 1: Japanese Patent Application Publication No. 2005-259266
Here, when performing the repair analysis, the test apparatus sequentially reads the fail data from the AFM and counts the number of fail cells (RFC) for each row address and the number of fail cells (CFC) for each column address in the memory under test. The counting process for obtaining the RFC and the CFC is preferably performed quickly in order to shorten the repair analysis time between tests and improve the overall throughput. Accordingly, the test apparatus is preferably formed using a high-speed memory, such as an SRAM, as the counter circuit for obtaining the RFC and the CFC.
In recent years, however, the capacity of the memory under test has increased. Accordingly, the test apparatus must have larger memory capacity for storing the RFC and the CFC, according to the capacity of the memory under test.
However, a high-capacity SRAM is expensive and difficult to obtain. Accordingly, a test apparatus in which the memory capacity is increased to store the RFC and the CFC is more expensive.